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1 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information n fast 40mbps differential transmission rates n improved esd tolerance for analog i/os n internal transceiver termination resistors for v.11 and v.35 n interface modes: 3 rs-232 (v.28) 3 eia-530 (v.10 & v.11) 3 x.21 (v.11) 3 eia-530a (v.10 & v.11) 3 rs-449/v.36 (v.10 & v.11) 3 v.35 n protocols are software selectable with 3-bit word n eight (8) drivers and eight (8) receivers n termination network disable option n internal line or digital loopback for diagnostic testing n adheres to net1/net2 and tbr-2 compliancy requirements n easy flow-through pinout n +5v only operation n individual driver and receiver enable/disable controls n operates in either dte or dce mode SP508 rugged 40mbps, 8 channel multiprotocol transceiver with programmable dce/dte and termination resistors description the SP508 is a monolithic device that supports eight (8) popular serial interface standards for wide area network (wan) connectivity. the SP508 is fabricated using a low power bicmos process technology, and incorporates a sipex regulated charge pump allowing +5v only operation. sipex's patented charge pump provides a regulated output of +5.8v, which will provide enough voltage for compliant operation in all modes. eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. the SP508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than four capacitors used for the internal charge pump. all necessary termination is integrated within the SP508 and is switchable when v.35 drivers and v.35 receivers, or when v.11 receivers are used. the SP508 provides the controls and transceiver availability for operating as either a dte or dce. additional features with the SP508 include internal loopback that can be initiated in any of the operating modes by use of the loopback pin. while in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. the SP508 also includes a latch enable pin with the driver and receiver address decoder. the internal v.11 or v.35 termination can be switched off using a control pin (term_off) for monitoring applications. all eight (8) drivers and receivers in the SP508 include separate enable pins for added convenience. the SP508 is ideal for wan serial ports in networking equipment such as routers, access concentrators, network muxes, dsu/csu's, networking test equipment, and other access devices. applicable u.s. patents-5,306,954; and others patents pending ?
2 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information specifications t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions logic inputs v il 0.8 volts v ih 2.0 volts logic outputs v ol 0.4 volts i out = C3.2ma v oh 2.4 volts i out = 1.0ma v.28 driver dc parameters outputs open circuit voltage 15 volts per figure 1 loaded voltage 5.0 15 volts per figure 2 short-circuit current 100 ma per figure 4 power-off impedance 300 w per figure 5 ac parameters v cc = +5v for ac parameters outputs transition time 1.5 m s per figure 6 ; +3v to -3v instantaneous slew rate 30 v/ m s per figure 3 propagation delay t phl 0.5 1 5 m s t plh 0.5 1 5 m s max.transmission rate 120 230 kbps v.28 receiver dc parameters inputs input impedance 3 7 k w per figure 7 open-circuit bias +2.0 volts per figure 8 high threshold 1.7 3.0 volts low threshold 0.8 1.2 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 100 500 ns t plh 50 100 500 ns absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ................................................................................................ +7v input voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ............................................. -0.3v to (v cc +0.5v) receivers ........................................................... 15.5v output voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ................................................................... 15v receivers ........................................ -0.3v to (v cc +0.5v) storage temperature ................................................ -65 c to +150 c power dissipation ................................................................. 1520mw (derate 19.0mw/ c above +70 c) package derating: ? ja ................................................................................................................. 52.7 c/w ? jc .................................................................................................................... 6.5 c/w storage considerations due to the relatively large package size of the 100-pin quad flat- pack, storage in a low humidity environment is preferred. large high density plastic packages are moisture sensitive and should be stored in dry vapor barrier bags. prior to usage, the parts should remain bagged and stored below 40 c and 60%rh. if the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%rh. if the above conditions cannot be followed, the parts should be baked for four hours at 125 c in order to remove moisture prior to soldering. sipex ships the 100-pin lqfp in dry vapor barrier bags with a humidity indicator card and desiccant pack. the humidity indicator should be below 30%rh.
3 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information specifications t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions v.28 receiver (continued) ac parameters (cont.) max.transmission rate 120 230 kbps v.10 driver dc parameters outputs open circuit voltage 4.0 6.0 volts per figure 9 test-terminated voltage 0.9v oc volts per figure 10 short-circuit current 150 ma per figure 11 power-off current 100 m a per figure 12 ac parameters v cc = +5v for ac parameters outputs transition time 200 ns per figure 13 ; 10% to 90% propagation delay t phl 30 100 500 ns t plh 30 100 500 ns max.transmission rate 120 kbps v.10 receiver dc parameters inputs input current C3.25 +3.25 ma per figures 14 and 15 input impedance 4 k w sensitivity 0.3 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 ns t plh 50 ns max.transmission rate 120 kbps v.11 driver dc parameters outputs open circuit voltage 6.0 volts per figure 16 test terminated voltage 2.0 volts per figure 17 0.5v oc 0.67v oc volts balance 0.4 volts per figure 17 offset +3.0 volts per figure 17 short-circuit current 150 ma per figure 18 power-off current 100 m a per figure 19 ac parameters v cc = +5v for ac parameters outputs transition time 10 ns per figures 21 and 36 ; 10% to 90% propagation delay using c l = 50pf; t phl 30 50 ns per figures 33 and 36 t plh 30 50 ns per figures 33 and 36 differential skew 10 ns per figures 33 and 36 max.transmission rate 40 mbps v.11 receiver dc parameters inputs common mode range C7 +7 volts sensitivity 0.2 volts
4 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information specifications t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions v.11 receiver (continued) dc parameters (cont.) input current C3.25 3.25 ma per figure 20 and 22 ; power on or off current w/ 100 w termination 60.75 ma per figure 23 and 24 input impedance 4 k w ac parameters v cc = +5v for ac parameters propagation delay using c l = 50pf; t phl 30 50 ns per figures 33 and 38 t plh 30 50 ns per figures 33 and 38 skew 5 ns per figure 33 max.transmission rate 40 mbps v.35 driver dc parameters outputs test terminated voltage 0.44 0.66 volts per figure 25 offset 0.6 volts per figure 25 output overshoot -0.2v st +0.2v st volts per figure 25 ; v st = steady state value source impedance 50 150 w per figure 27 ; z s = v 2 /v 1 x 50 short-circuit impedance 135 165 w per figure 28 ac parameters v cc = +5v for ac parameters outputs transition time 7 20 ns per figure 29 ; 10% to 90% propagation delay t phl 30 50 ns per figures 33 and 36 ; c l = 20pf t plh 30 50 ns per figures 33 and 36 ; c l = 20pf differential skew 5 ns per figures 33 and 36 ; c l = 20pf max.transmission rate 40 mbps v.35 receiver dc parameters inputs sensitivity 50 +100 mv source impedance 90 110 w per figure 30 ; z s = v 2 /v 1 x 50 w short-circuit impedance 135 165 w per figure 31 ac parameters v cc = +5v for ac parameters propagation delay t phl 30 50 ns per figures 33 and 38 ; c l = 20pf t plh 30 50 ns per figures 33 and 38 ; c l = 20pf skew 3 ns per figure 33 ; c l = 20pf max.transmission rate 40 mbps transceiver leakage currents driver output 3-state current 100 500 m a per figure 32 ; drivers disabled rcvr output 3-state current 1 10 m at x & r x disabled, 0.4v - v o - 2.4v power requirements v cc 4.75 5.00 5.25 volts i cc (shutdown mode) 1 m a all i cc values are with v cc = +5v (v.28/rs-232) 95 ma f in = 120kbps; drivers active & loaded (v.11/rs-422) 230 ma f in = 10mbps; drivers active & loaded (eia-530 & rs-449) 270 ma f in = 10mbps; drivers active & loaded (v.35) 170 ma v.35 @ f in = 10mbps, v.28 @ 20kbps (eia-530a) 200 ma f in = 10mbps; drivers active & loaded
5 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information other ac characteristics t a = +25 c and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions driver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.11 5.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed t pzh ; tri-state to output high 0.11 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed t plz ; output low to tri-state 0.05 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed t phz ; output high to tri-state 0.05 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.07 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed t pzh ; tri-state to output high 0.05 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed t plz ; output low to tri-state 0.55 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed t phz ; output high to tri-state 0.12 2.0 m sc l = 100pf, fig. 34 & 40 ; s 2 closed rs-422/v.11 t pzl ; tri-state to output low 0.04 10.0 m sc l = 100pf, fig. 34 & 37 ; s 1 closed t pzh ; tri-state to output high 0.05 2.0 m sc l = 100pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 m sc l = 15pf, fig. 34 & 37 ; s 1 closed t phz ; output high to tri-state 0.11 2.0 m sc l = 15pf, fig. 34 & 37 ; s 2 closed v.35 t pzl ; tri-state to output low 0.85 10.0 m sc l = 100pf, fig. 34 & 37 ; s 1 closed t pzh ; tri-state to output high 0.36 2.0 m sc l = 100pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.06 2.0 m sc l = 15pf, fig. 34 & 37 ; s 1 closed t phz ; output high to tri-state 0.05 2.0 m sc l = 15pf, fig. 34 & 37 ; s 2 closed receiver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.05 2.0 m sc l = 100pf, fig. 35 & 40 ; s 1 closed t pzh ; tri-state to output high 0.05 2.0 m sc l = 100pf, fig. 35 & 40 ; s 2 closed t plz ; output low to tri-state 0.65 2.0 m sc l = 100pf, fig. 35 & 40 ; s 1 closed t phz ; output high to tri-state 0.65 2.0 m sc l = 100pf, fig. 35 & 40 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.04 2.0 m sc l = 100pf, fig. 35 & 40 ; s 1 closed t pzh ; tri-state to output high 0.03 2.0 m sc l = 100pf, fig. 35 & 40 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 m sc l = 100pf, fig. 35 & 40 ; s 1 closed t phz ; output high to tri-state 0.03 2.0 m sc l = 100pf, fig. 35 & 40 ; s 2 closed
6 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information other ac characteristics (continued) t a = +25 c and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions rs-422/v.11 t pzl ; tri-state to output low 0.04 2.0 m sc l = 100pf, fig. 35 & 39 ; s 1 closed t pzh ; tri-state to output high 0.03 2.0 m sc l = 100pf, fig. 35 & 39 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 m sc l = 15pf, fig. 35 & 39 ; s 1 closed t phz ; output high to tri-state 0.03 2.0 m sc l = 15pf, fig. 35 & 39 ; s 2 closed v.35 t pzl ; tri-state to output low 0.04 2.0 m sc l = 100pf, fig. 35 & 39 ; s 1 closed t pzh ; tri-state to output high 0.03 2.0 m sc l = 100pf, fig. 35 & 39 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 m sc l = 15pf, fig. 35 & 39 ; s 1 closed t phz ; output high to tri-state 0.03 2.0 m sc l = 15pf, fig. 35 & 39 ; s 2 closed transceiver to transceiver skew (per figures 32, 33, 36, 38) rs-232 driver 100 ns [ (t phl ) tx1 C (t phl ) txn ] 100 ns [ (t plh ) tx1 C (t plh ) txn ] rs-232 receiver 20 ns [ (t phl ) rx1 C (t phl ) rxn ] 20 ns [ (t phl ) rx1 C (t phl ) rxn ] rs-422 driver 2 ns [ (t phl ) tx1 C (t phl ) txn ] 2ns[ (t plh ) tx1 C (t plh ) txn ] rs-422 receiver 2 ns [ (t phl ) rx1 C (t phl ) rxn ] 3ns[ (t phl ) rx1 C (t phl ) rxn ] rs-423 driver 5 ns [ (t phl ) tx2 C (t phl ) txn ] 5ns[ (t plh ) tx2 C (t plh ) txn ] rs-423 receiver 5 ns [ (t phl ) rx2 C (t phl ) rxn ] 5ns[ (t phl ) rx2 C (t phl ) rxn ] v.35 driver 2 ns [ (t phl ) tx1 C (t phl ) txn ] 2ns[ (t plh ) tx1 C (t plh ) txn ] v.35 receiver 2 ns [ (t phl ) rx1 C (t phl ) rxn ] 2ns[ (t phl ) rx1 C (t phl ) rxn ]
7 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information a v oc c a v t c 3k w a v t c 7k w oscilloscope scope used for slew rate measurement. a i sc c a c v cc = 0v 2v i x a c 3k w 2500pf oscilloscope figure 1. v.28 driver output open circuit voltage figure 2. v.28 driver output loaded voltage figure 3. v.28 driver output slew rate figure 4. v.28 driver output short-circuit current figure 6. v.28 driver output rise/fall times figure 5. v.28 driver output power-off impedance test circuits
8 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 7. v.28 receiver input impedance a c i ia 15v a c v oc figure 8. v.28 receiver input open circuit bias a v oc 3.9k w c a v t 450 w c a c 0.25v v cc = 0v i x a i sc c figure 9. v.10 driver output open-circuit voltage figure 10. v.10 driver output test terminated voltage figure 12. v.10 driver output power-off current figure 11. v.10 driver output short-circuit current
9 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 13. v.10 driver output transition time figure 14. v.10 receiver input current a 450 w c oscilloscope a c i ia 10v figure 15. v.10 receiver input iv graph figure 16. v.11 driver output open-circuit voltage a b v oc 3.9k w v oca v ocb c a b v t 50 w v os c 50 w a b c i sa i sb figure 17. v.11 driver output test terminated voltage figure 18. v.11 driver output short-circuit current +3.25ma -3.25ma +10v +3v -3v -10v maximum input current versus voltage v.10 receiver
10 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information a b c i xa 0.25v a b c i xb 0.25v v cc = 0v v cc = 0v a b c i ia 10v c i ib 10v a b figure 19. v.11 driver output power-off current figure 20. v.11 receiver input current figure 21. v.11 driver output rise/fall time figure 22. v.11 receiver input iv graph a b 50 w c 50 w 50 w v e oscilloscope +3.25ma -3.25ma +10v +3v -3v -10v maximum input current versus voltage v.11 receiver
11 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 23. v.11 receiver input current w/ termination figure 24. v.11 receiver input graph w/ termination figure 25. v.35 driver output test terminated voltage figure 26. v.35 driver output offset voltage figure 27. v.35 driver output source impedance a b 50 w c 50 w v t v os a b v 2 50 w c 24khz, 550mv p-p sine wave v 1 a b 50 w c 50 w v t v os i [ma] = v [v] / 0.1 +6v +3v -3v -6v maximum input current versus voltage v.11 receiver w/ optional cable termination (100ohms to 150ohms) i [ma] = v [v] / 0.1 i [ma] = (v [v] - 3) / 4.0 i [ma] = (v [v] - 3) / 4.0 a b c i ia 6v 100 w to 150 w c i ib 6v a b 100 w to 150 w
12 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 32. driver output leakage current test figure 33. driver/receiver timing test circuit figure 30. v.35 receiver input source impedance figure 29. v.35 driver output rise/fall time figure 31. v.35 receiver input short-circuit impedance figure 28. v.35 driver output short-circuit impedance a b c i sc 2v a b c 50 w oscilloscope 50 w 50 w a b c i sc 2v c l1 15pf r out a b a b t in c l2 a b v 2 50 w c 24khz, 550mv p-p sine wave v 1 a b i zsc logic 1 12v 0 00 0 dec 3 dec 2 dec 1 dec 0 v cc = 0v v cc any one of the three conditions for disabling the driver.
13 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 34. driver timing test load circuit figure 35. receiver timing test load circuit 500 w c l output under test s 1 s 2 v cc 1k w 1k w c rl receiver output s 1 s 2 test point v cc figure 36. driver propagation delays figure 37. driver enable and disable times figure 38. receiver propagation delays +3v 0v driver input a b driver output v o + differential output v b C v a 0v v o C 1.5v 1.5v t plh t r t f f > 10mhz; t r < 10ns; t f < 10ns v o 1/2v o 1/2v o t phl t dplh t dphl t skew = | t dplh - t dphl | +3v 0v 5v v ol a, b 0v 1.5v 1.5v t zl t zh v oh a, b 2.3v 2.3v t lz t hz 0.5v 0.5v output normally low output normally high mx or tx_enable v oh v ol receiver out (v oh - v ol )/2 (v oh - v ol )/2 t plh f > 10mhz; t r < 10ns; t f < 10ns output v 0d2 + v 0d2 C a C b 0v 0v t phl input t skew = | t phl - t plh |
14 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 39. receiver enable and disable times figure 40. v.28 (rs-232) and v.10 (rs-423) driver enable and disable times +3v 0v r x _enable 5v 0v 1.5v 1.5v t zl t zh f = 1mhz; t r < 10ns; t f < 10ns receiver out 1.5v 1.5v t lz t hz 0.5v 0.5v output normally low output normally high v il v ih receiver out +3v 0v tx_enable 1.5v 1.5v t zl f = 60khz; t r < 10ns; t f < 10ns t out t lz output low 0v +3v 0v v oh 1.5v 1.5v t zh f = 60khz; t r < 10ns; t f < 10ns t out v oh - 0.5v t hz output high 0v tx_enable v oh - 0.5v v ol - 0.5v v ol - 0.5v v ol
15 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 41. typical v.28 driver output waveform figure 42. typical v.10 driver output waveform figure 43. typical v.11 driver output waveform figure 44. typical v.35 driver output waveform
16 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information pinout pin assignments pin 1 v cc +5v power supply input. pin 2 gnd signal ground. pin 3 sden t x d driver enable input. pin 4 tten txce driver enable input. pin 5 sten st driver enable input. pin 6 rsen rts driver enable input. pin 7 tren dtr driver enable input. pin 8 rrcen dcd dce driver enable input. pin 9 rlen rl driver enable input. pin 10 llen ll driver enable input. pin 11 rden r x d receiver enable input. pin 12 rten r x t receiver enable input. pin 13 t x cen t x c receiver enable input. pin 14 csen cts receiver enable input. pin 15 dmen dsr receiver enable input. pin16 rrten dcd dte receiver enable input. pin 17 icen ri receiver enable input. pin 18 tmen tm receiver enable input. vcc 1 gnd 2 sden 3 tten 4 sten 5 rsen 6 tren 7 rrcen 8 rlen 9 llen 10 rden 11 rten 12 txcen 13 csen 14 dmen 15 rrten 16 icen 17 tmen 18 d0 19 d1 20 d2 21 term_off 22 d_latch 23 n/c 24 gnd 25 vcc 26 loopback 27 txd 28 txce 29 st 30 dtr 31 rts 32 dcd_dce 33 rl 34 ll 35 rxd 36 rxc 37 txc 38 cts 39 dsr 40 dcd_dte 41 ri 42 tm 43 gnd 44 vcc 45 v35rgnd 46 rd(b) 47 rd(a) 48 rt(b) 49 rt(a) 50 75 tr(a) 74 gnd 73 vdd 72 c1+ 71 vcc 70 c2+ 69 c1- 68 gnd 67 c2- 66 vss 65 rl(a) 64 vcc 63 ll(a) 62 tm(a) 61 ic(a) 60 rrt(a) 59 rrt(b) 58 v10gnd 57 dm(a) 56 dm(b) 55 cs(a) 54 cs(b) 53 txc(a) 52 gnd 51 txc(b) 100 sd(b) 99 v35tgnd1 98 vcc 97 sd(a) 96 gnd 95 tt(b) 94 v35tgnd2 93 vcc 92 tt(a) 91 gnd 90 st(b) 89 v35tgnd3 88 vcc 87 st(a) 86 gnd 85 rs(b) 84 vcc 83 rs(a) 82 gnd 81 rrc(a) 80 vcc 79 rrc(b) 78 tr(b) 77 vcc 76 n/c SP508 pin 19 d0 mode select input. pin 20 d1 mode select input. pin 21 d2 mode select input. pin 22 term_off termination disable input. pin 23 d_latch decoder latch input. pin 24 n/c no connection. pin 25 gnd signal ground. pin 26 v cc +5v power supply input. pin 27loopbackloopback mode enable input. pin 28 txd txd driver ttl input. pin 29 txce txce driver ttl input. pin 30 st st driver ttl input. pin 31 rts rts driver ttl input. pin 32 dtr dtr driver ttl input. pin 33 dcd_dce dcd dce driver ttl input. pin 34 rl rl driver ttl input. pin 35 ll ll driver ttl input. pin 36 rxd rxd receiver ttl output. pin 37 rxc rxc receiver ttl output. pin 38 txc txc receiver ttl output. pin 39 cts cts receiver ttl output. pin 40 dtr dsr receiver ttl output. pin 41 dcd_dte dcd dte receiver ttl output. pin 42 ri ri receiver ttl output. pin 43 tm tm receiver ttl output. pin 44 gnd signal ground. pin 45 v cc +5v power supply input. pin 46 v35rgnd receiver termination reference. pin 47 rd(b) rxd non-inverting input.
17 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information pin 48 rd(a) rxd inverting input. pin 49 rt(b) rxt non-inverting input. pin 50 rt(a) rxt inverting input. pin 51 txc(b) txc non-inverting input. pin 52 gnd signal ground. pin 53 txc(a) txc inverting input. pin 54 cs(b) cts non-inverting input. pin 55 cs(a) cts inverting input. pin 56 dm(b) dsr non-inverting input. pin 57 dm(a) dsr inverting input. pin 58 v10gnd v.10 r x reference node. pin 59 rrt(b) dcd dte non-inverting input. pin 60 rrt(a) dcd dte inverting input. pin 61 ic(a) ri receiver input. pin 62 tm(a) tm receiver input. pin 63 ll(a) ll driver output. pin 64 v cc +5v power supply input. pin 65 rl(a) rl driver output. pin 66 v ss -2 x v cc charge pump output. pin 67 c2- charge pump capacitor. pin 68 gnd signal ground. pin 69 c1- charge pump capacitor. pin 70 c2+ charge pump capacitor. pin 71 v cc +5v power supply input. pin 72 c1+ charge pump capacitor. pin 73 v dd 2 x v cc charge pump output. pin 74 gnd signal ground. pin 75 tr(a) dtr inverting output. pin 76 n/c no connection. pin 77 v cc +5v power supply input. pin 78 tr(b) dtr non-inverting output. pin 79 rrc(b) dcd dce non-inverting output. pin 80 v cc +5v power supply input. pin 81 rrc(a) dcd dce inverting output. pin 82 gnd signal ground. pin 83 rs(a) rts inverting output. pin 84 v cc +5v power supply input. pin 85 rs(b) rts non-inverting output. pin 86 gnd signal ground. pin 87 st(a) st inverting output. pin 88 v cc +5v power supply input. pin 89 v35tgnd3 st termination reference. pin 90 st(b) st non-inverting output. pin 91 gnd signal ground. pin 92 tt(a) txce inverting output. pin 93 v cc +5v power supply input. pin 94 v35tgnd2 txce termination reference. pin 95 tt(b) txce non-inverting output. pin 96 gnd signal ground. pin 97 sd(a) txd inverting output. pin 98 v cc - +5v power supply input. pin 99 v35tgnd1 txd termination reference. pin 100 sd(b) txd non-inverting output.
18 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information table 1. driver mode selection table 2. receiver mode selection SP508 driver table SP508 receiver table n i p t u p t u o r e v i r d e d o m 5 3 . v 0 3 5 - a i e e d o m 2 3 2 - s r e d o m ) 8 2 . v ( a 0 3 5 - a i e e d o m 9 4 4 - s r e d o m ) 6 3 . v ( e d o m 1 2 . x ) 1 1 . v ( n w o d t u h s d e t s e g g u s l a n g i s e d o m ) 2 d , 1 d , 0 d ( 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 t 1 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( d x t t 1 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( d x t t 2 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c x t t 2 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c x t t 3 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c d _ c x t t 3 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c d _ c x t t 4 ) a ( t u o8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( s t r t 4 ) b ( t u oz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( s t r t 5 ) a ( t u o8 2 . v1 1 . v8 2 . v0 1 . v1 1 . v1 1 . vz - h g i h) a ( r t d t 5 ) b ( t u oz - h g i h1 1 . vz - h g i hz - h g i h1 1 . v1 1 . vz - h g i h) b ( r t d t 6 ) a ( t u o8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c d _ d c d t 6 ) b ( t u oz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c d _ d c d t 7 ) a ( t u o8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hl r t 8 ) a ( t u o8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hl l
19 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 45. SP508 block diagram txd sd(a) v35tgnd1 sd(b) sden v cc v dd c1- v ss c1+ +5v (decoupling capacitor not shown) 1 m f regulated charge pump SP508 txce tt(a) v35tgnd2 tt(b) tten st st(a) v35tgnd3 st(b) sten rd(a) rxd rden rd(b) rt(a) rxc rten rt(b) txc(a) txc txcen txc(b) cs(a) cts csen cs(b) dm(a) dsr dmen dm(b) rrt(a) dcd_dte rrten rrt(b) tm tm tmen rts rs(a) rs(b) rsen dtr tr(a) tr(b) tren dcd_dce rrc(a) rrc(b) rrcen ll ll(a) llen c2- c2+ 1 m f 1 m f 1 m f gnd d0 d1 d2 term-off d-latch v.10-gnd v.35 mode tx enable 51ohms 51ohms 124ohms v.35 driver termination network v.35 mode rx enable 51ohms 51ohms 124ohms receiver termination network v.11 mode rl rl(a) rlen ic ri icen v35rgnd loopback
20 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information features the SP508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. the SP508 offers the hardware interface modes for rs-232 (v.28), rs-449/v.36 (v.11 and v.10), eia-530 (v.11 and v.10), eia-530a (v.11 and v.10), v.35 (v.35 and v.28) and x.21(v.11). the interface mode selection is done via three control pins, which can be latched via microprocessor control. the SP508 has eight drivers, eight receivers, and sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted, individual termination resistor ground paths, separate driver and receiver ground outputs, enhanced esd protection on driver outputs and receiver inputs. theory of operation the SP508 device is made up of 1) the drivers, 2) the receivers, 3) a charge pump, 4) dte/dce switching algorithm, and 5) control logic. drivers the SP508 has eight enhanced independent drivers. control for the mode selection is done via a three- bit control word into d0, d1, and d2. the drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. as the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. the mode of each driver in the different interface modes that can be selected is shown in table 1 . there are four basic types of driver circuits C itu-t-v.28 (rs-232), itu-t-v.10 (rs-423), itu-t-v.11 (rs-422), and ccitt-v.35. the v.28 (rs-232) drivers output single-ended signals with a minimum of +5v (with 3k w & 2500pf loading), and can operate over 120kbps. since the sp550 uses a charge pump to generate the rs-232 output rails, the driver outputs will never exceed +10v. the v.28 driver architecture is similar to sipex's standard line of rs-232 transceivers. the rs-423 (v.10) drivers are also single-ended signals which produce open circuit v ol and v oh measurements of +4.0v to +6.0v. when terminated with a 450 w load to ground, the driver output will not deviate more than 10% of the open circuit value. this is in compliance of the itu v.10 specification. the v.10 (rs-423) drivers are used in rs-449/v.36, eia-530, and eia-530a modes as category ii signals from each of their corresponding specifications. the v.10 driver can transmit over 1mbps if necessary. the third type of drivers are v.11 (rs-422) differential drivers. due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. the advantage is evident over high speeds and long transmission lines. the strength of the driver outputs can produce differential signals that can maintain +2v differential output levels with a load of 100 w . the signal levels and drive capability of these drivers allow the drivers to also support rs-485 requirements of +1.5v differential output levels with a 54 w load. the strength allows the SP508 differential driver to drive over long cable lengths with minimal signal degradation. the v.11 drivers are used in rs-449, eia-530, eia-530a and v.36 modes as category i signals which are used for clock and data. sipex's new driver design over its predecessors allow the SP508 to operate over 40mbps for differential transmission.
21 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information the fourth type of drivers are v.35 differential drivers. there are only three available on the sp550 for data and clock (txd, txce, and txc in dce mode). these drivers are current sources that drive loop current through a differential pair resulting in a 550mv differential voltage at the receiver. these drivers also incorporate fixed termination networks for each driver in order to set the v oh and v ol depending on load conditions. this termination network is basically a y configuration consisting of two 51 w resistors connected in series and a 124 w resistor connected between the two 50 w resistors and a v35tgnd output. each of the three drivers and its associated termination will have its own v35tgnd output for grounding convenience. filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. the drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable dte/dce. the enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on figure 45 . the enable pins have internal pull-up and pull- down devices, depending on the active polarity of the receiver, that enable the driver upon power if the enable lines are left floating. during disabled conditions, the driver outputs will be at a high impedance 3-state. the driver inputs are both ttl or cmos compatible. all driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic low (0). unused driver inputs can be left floating. the internal pull-up resistor value is approximately 500k w . receivers the SP508 has eight enhanced independent receivers. control for the mode selection is done via a three-bit control word that is the same as the driver control word. therefore, the modes for the drivers and receivers are identical in the application. like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. as the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. table 1 shows the mode of each receiver in the different interface modes that can be selected. there are two basic types of receiver circuitsitu-t-v .28 (rs-232) and itu-t-v.11, (rs-422). the rs-232 (v.28) receiver is single-ended and accepts rs-232 signals from the rs-232 driver. the rs-232 receiver has an operating voltage range of +15v and can receive signals downs to +3v. the input sensitivity complies with rs-232 and v .28 at +3v. the input impedance is 3 w to 7k w in accordance to rs-232 and v .28. the receiver output produces a ttl/cmos signal with a +2.4v minimum for a logic 1 and a +0.8v maximum for a logic 0. the rs-232 (v.28) protocol uses these receivers for all data, clock and control signals. they are also used in v.35 mode for control line signals: cts, dsr, ll, and rl. the rs-232 receivers can operate over 120kbps. the second type of receiver is a differential type that can be configured internally to support itu-t-v.10 and ccitt-v.35 depending on its input conditions. this receiver has a typical input impedance of 10k w and a differential threshold of less than +100mv, which complies with the itu-t-v.11 (rs-422) specifications. v.11 receivers are used in rs-449/v.36, eia-530, eia-530a and x.21 as category i signals for receiving clock, data, and some control line signals not covered by category ii v.10 circuits. the differential v.11 transceiver has improved architecture that allows over 40mbps transmission rates. for receivers dedicated for data and clock (rxd, rxc, txc) incorporate internal termination for v.11. the termination resistor is typically 120 w connected between the a and b inputs. the termination is essential for minimizing crosstalk and signal reflection over the transmission line . the minimum value is guaranteed to exceed 100 w , thus complying with the v.11 and rs-422 specifications. this resistor is invoked when the receiver is operating as a v.11 receiver, in modes eia-530, eia-530a, rs-449/v.36, and x.21.
22 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information the same receivers also incorporate a termination network internally for v.35 applications. for v.35, the receiver input termination is a y termination consisting of two 51 w resistors connected in series and a 124 w resistor connected between the two 50 w resistors and v35rgnd output. the v35rgnd is usually grounded. the receiver itself is identical to the v.11 receiver. the differential receivers can be configured to be itu-t-v.10 single-ended receivers by internally connecting the non-inverting input to ground. this is internally done by default from the decoder. the non-inverting input is rerouted to v10gnd and can be grounded separately. the itu-t-v.10 receivers can operate over 1mbps and are used in rs-449/v.36, e1a-530, e1a-530a and x.21 modes as category ii signals as indicated by their corresponding specifications. all receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex configurations. the enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on figure 45 . the receivers enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. during disabled conditions, the receiver outputs will be at a high impedance state. if the receiver is disabled any associated termination is also disconnected from the inputs. all receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. for single-ended v.28 and v.10 receivers, there are internal 5k w pull-down resistors on the inputs which produces a logic high (1) at the receiver outputs. the differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic high (1) at the receiver output. charge pump the charge pump is a sipex -patented design (5,306,954) and uses a unique approach compared to older less-efficient designs. the charge pump still requires four external capacitors, but uses four-phase voltage shifting technique to attain symmetrical power supplies. the charge pump v dd and v ss outputs are regulated to +5.8v and -5.8v, respectively. there is a free-running oscillator that controls the four phases of the voltage shifting. a description of each phase follows. phase 1 __v ss charge storage during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to v cc . c+ is then switched to ground and the charge in c 1 - is transferred to c 2 -. since c 2 + is connected to v cc , the voltage potential across capacitor c 2 is now 2 x v cc . phase 2 v ss transfer phase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to ground, and transfers the negative generated voltage to c 3 . this generated voltage is regulated to C5.8v. simultaneously, the positive side of the capacitor c 1 is switched to v cc and the negative side is connected to ground. phase 3 v dd charge storage the third phase of the clock is identical to the first phasethe charge transferred in c 1 produces Cv cc in the negative terminal of c 1 which is applied to the negative side of the capacitor c 2 . since c 2 + is at v cc , the voltage potential across c 2 is 2 x v cc . phase 4 v dd transfer the fourth phase of the clock connects the negative terminal of c 2 to ground, and transfers the generated 5.8v across c 2 to c 4 , the v dd storage capacitor. this voltage is regulated to +5.8v. at the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor c 1 is switched to v cc and the negative side is connected to ground, and the cycle begins again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.
23 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information since both v + and v - are separately generated from v cc ; in a no-load condition v + and v - will be symmetrical. older charge pump approaches that generate v - from v + will show a decrease in the magnitude of v - compared to v + due to the inherent inefficiencies in the design. the clock rate for the charge pump typically operates at 250khz. the external capacitors can be as low as 1 m f with a 16v breakdown voltage rating. term_off function the SP508 contains a term_off pin that disables all three receiver input termination networks regardless of mode. this allows the device to be used in monitor mode applications typically found in networking test equipment. the term_off pin internally contains a pull-down device with an impedance of over 500k w , which will default in a on condition during power-up if v.35 receivers are used. the individual receiver enable line and the shutdown mode from the decoder will disable the termination regardless of term_off. loopback function the SP508 contains a loopback pin that invokes a loopback path. this loopback path is illustrated in figure 50 . loopback has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. during loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. decoder and d_latch function the SP508 contains a d_latch pin that latches the data into the d0, d1, and d2 decoder inputs. if tied to a logic low (0), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP508 accordingly. if tied to a logic high(1), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic low. there are internal pull-up devices on d0, d1, and d2, which allow the device to be in shutdown mode (111) upon power up. however , if the device is powered -up with the d_latch at a logic high, the decoder state of the SP508 will be undefined. esd tolerance the SP508 device incorporates ruggedized esd cells on all driver output and receiver input pins. the esd structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. actual esd figures will be disclosed in the final data sheet. ctr1/ctr2 european compliancy as with all of sipexs previous multi-protocol serial transceiver ics the drivers and receivers have been designed to meet all the requirements to net1/net2 and tbr2 in order to meet ctr1/ctr2 compliancy. the SP508 is also tested in-house at sipex and adheres to all the net1/2 physical layer testing and the itu series v specifications before shipment. please note that although the SP508 , as with its predecessors, adhere to ctr1/ctr2 compliancy testing, any complex or unusual configuration should be double-checked to ensure ctr1/ctr2 compliance. consult the factory for details.
24 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 46. SP508 loopback path sd(a) sd(b) rd(a) rd(b) tt(a) tt(b) rt(a) rt(b) txd rxd txce rxc st(a) st(b) txc(a) txc(b) st txc rs(a) rs(b) cs(a) cs(b) tr(a) tr(b) dm(a) dm(b) rts cts dtr dsr rrc(a) rrc(b) rrt(a) rrt(b) dcd_dce dcd_dte rl(a) ic rl ri ll(a) tm(a) ll tm
25 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information figure 47. SP508 typical operating configuration to serial port connector with dce/dte programmability 20 (v.11, v.28) dtr_dsr_a 23 (v.11) dtr_dsr_b 1 m f 1 m f 1 m f v cc v dd c1- c2- v ss c1+ c2+ 1 m f SP508cf txd txce st rts dtr dcd_dce rl rxc txc cts dsr dcd_dte ri tm 10 m f m db-26 serial port connector pins signal (dte_dce) 2 (v.11, v.35, v.28) txd_rxd_a 14 (v.11, v.35) txd_rxd_b 11 (v.11, v.35) txce_txc_b 25 (v.10, v.28) ll_tm 15 (v.11, v.35, v.28) *txc_rxc_a 12 (v.11, v.35) *txc_rxc_b sden 24 (v.11, v.35, v.28) txce_txc_a 3 (v.11, v.35, v.28) rxd_txd_a 16 (v.11, v.35) rxd_txd_b 8 (v.11, v.28) dcd_dcd_a 10 (v.11) dcd_dcd_b typical SP508 db-26 serial port configuration customer : title : date : doc. # : rev. 0 reference design schematic 233 south hillview dr. ? milpitas, ca. 95035 signal gnd (pins 7) 9 (v.11, v.35) rxc_txce_b 17 (v.11, v.35, v.28) rxc_txce_a llen sten gnd * - driver applies for dce only on pins 15 and 12. receiver applies for dte only on pins 15 and 12. +5v #103 (txd) #108 (dtr) #105 (rts) #141 (ll) #105 (rxd) #115 (rxc) #106 (cts) #107 (dsr) #109 (dcd) dte i/o lines represented by double arrowhead signifies a bi-directional bus. input line output line #114 (txc) #113 (txce) #109 (dcd) dce ll rxd tten tren rsen rrcen rlen rden tmen txcen rten dmen csen rrten icen v10_gnd v35tgnd1 v35tgnd2 v35tgnd3 v35rgnd term_off d_latch d0 d1 d2 charge pump section transceiver section logic section +5v 21 (v.10, v.28) rl_ri 22 (v.10, v.28) ri_rl 18 (v.10, v.28) ll_tm #125 (ri) #142 (tm) #140 (rl) dce/dte driver applies for dce only on pins 8 and 10. receiver applies for dte only on pins 8 and 10. loopback +5v 19 (v.11) rts_cts_b 4 (v.11, v.28) rts_cts_a 6 (v.11, v.28) dsr_dtr_a 22 (v.11) dsr_dtr_b 13 (v.11) cts_rts_b 5 (v.11, v.28) cts_rts_a
26 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information package: quad flatpack lqfp outline e (n-4)x a a2 0.05 s 12 a1 ddd m c a-b s d s b -c- seating plane c ccc -h- 02 2 03 s r1 01 (l1) l b b 00 gauge plane .25 11 r2 11 9 (b) 11 b1 11 c 11 c1 with plating 4x 1 2 3 bbb h aCb d 5 2 10 aaa c aCb d n 4x n / 4 tips 7 3 -a- e1/4 d1/4 6 -d- 3 d1/2 d/2 d1 5 2 d 4 a a -b- 3 -e- e1/2 e1 2 5 e 4 (see fig 2) see fig 4 -x- e/2 3 x = a, b or d even lead sides top view -x- x = a, b or d odd lead sides top view (b) 3 9 all dimensioning and tolerancing conforms to ansi y14.5m-1982. the top package body size may be smaller than the bottom package body size by as much as 0.15mm. datums and to be determined at datum plane to be determined at seating plane dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. details of pin 1 identifier are optional but must be located within the zone indicated. rectangular variations aha and bha have 38 and 26 leads on sides d and e respectively. rectangular variations ahb and bhb have 30 and 20 leads on sides d and e respectively. all dimensions are in millimeter. dimensions b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm.dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. exact shape of each corner is optional. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. a1 is defined as the distance from the seating plane to the lowest point of the package body. 1 2 3 4 5 6 7 8 9 10 11 12 a C b C d C C h C C c C ms-026 bed square s y m b o l n o t e min 1.40 0.05 1.35 nom 1.50 0.10 1.40 max 1.60 0.15 1.45 a a1 a2 d d1 e e1 n e b b1 r2 r1 00 01 02 03 s c c1 l l1 aaa bbb ccc ddd 16.00 bsc 14.00 bsc 16.00 bsc 14.00 bsc 100 0.50 bsc 0.17 0.17 0.08 0.08 0 o 0 o 11 o 11 o 0.20 0.09 0.09 0.45 0.22 0.20 C C 3.5 o C 12 o 12 o C C C 0.60 0.27 0.23 0.20 C 7 o C 13 o 13 o C 0.20 0.16 0.75 4 5, 2 4 5, 2 9 1.00 ref tolerance of form and position 0.20 0.20 0.08 0.08 note ref issue 1, 8 11 - 411 a
27 rev. 8/31/00 SP508 enhanced wan multiCmode serial transceiver ? copyright 2000 sipex corporation preliminary information ordering information model temperature range package types SP508cf ........................................................................... 0 c to +70 c ............................................................................. 100Cpin jedec lqfp corporation signal processing excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600

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